The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device with a block write function and a method for gating the columns thereof.
Advancement of technology for designing and fabricating a semiconductor memory device has made it possible to produce a highly integrated semiconductor memory device. In addition, it tends to be byte-wide having multifunctions so as to be used in a technical field such as graphic representation. Generally, a memory cell array consists of a plurality of memory cell blocks, which have a plurality of input/output line pairs. The reading or writing data from or into a memory cell is accomplished through the input/output line pair selected according to the address corresponding to the memory cell. For example, a semiconductor memory device of special use such as Video Random Access memory (Video RAM) performs block write function to write data into each of the memory cell blocks as a unit. Block write function requires column masking for masking the data of a specified memory cell.
FIG. 1 illustrates the conventional decoding structure of a conventional memory cell array of graphic use for performing the block write function to mask selected columns of a byte as a unit. It is assumed that one byte consists of eight bits and a data width is sixteen bits. In FIG. 1, a single memory cell block 2 is defined to have 256K bits (K=2.sup.10) and all the blocks include 2M bits (M=2.sup.20 ). Reference numerals 4A and 4B indicate the column decoders for decoding the data stored in the memory cell blocks. The column decoders 4A and 4B are to respectively decode the upper four and the lower four byte blocks. The decoding is accomplished in the so called half-activation to activate the odd or even numbered blocks 2. The adjacent blocks 2 commonly occupy a pair of input/output lines IO. However, the adjacent blocks in the boundary between the upper and the lower byte blocks include two or four pairs of input/output lines as shown in FIGS. 2A and 2B.
Meanwhile, the column decoders 4A and 4B shown in FIG. 3 are pre-decoders, one example of which is disclosed in Korean Patent Application No. 94-4126 filed in the name of the present applicant on Mar. 3, 1994. Referring to FIGS. 1 and 3, as is well known in the block write, the data Din inputted via a data input buffer (not shown) is a masking data for determining whether to enable or disable column selection lines CSL to control the column gates.
Referring to FIG. 3, if the block write signal .o slashed.BW a logic high, although the signals CA0, CA1, CA2 may be employed to make one of the eight combination signals DCA012 a high logic (which may be represented by the signal CSL or DQ as described in the above Patent Application), but the DCA012 is determined to have the high or low signal in logic according data input signal Din(Di (i=0, 1, . . . 7) shown in FIG. 3), so as to cause the column decoder to enable CSL thus simultaneously working a maximum eight memory cell blocks. Before performing the write command, the data is stored into the register of the memory device in advance, which register is called the color register in a semiconductor memory device used for graphics. For example, the inputted data Din is stored into the color register at LCR (load color register) timing or special WCBR timing in the respective case of a video RAM or a synchronous graphic dynamic RAM). Referring to FIG. 1 for illustrating the memory cell blocks with the data width of .times.16 indicating two bytes (one byte equals eight bits), the column masking is performed by two column decoder blocks each for controlling one of the two bytes (DQ0, . . . , 7, DQ8, . . . , 15). The column decoder includes DCA012 as shown in FIG. 3, and decoding blocks for decoding the addresses over CA3. The page depth is 256(2') from CA0 to CA7. The adjacent memory cell blocks commonly occupy a pair of data input/output lines IO and respectively output two DQs of the four DQs per one block of 256K.
The upper byte blocks (DQ8, . . . , 15) and the lower byte blocks (DQ0, . . . , 7) each are independently controlled by a respective column decoder requiring ten pairs of the data input/output lines IO. Meanwhile, four pairs of data input/output lines are required between the upper blocks and the lower blocks. In each of the upper and lower blocks, while the isolation gate may be used so that the activated 256K block and the inactivated 256 block commonly occupy the data input/output lines, as shown in FIG. 2A, it is impossible to commonly occupy the data input/output lines between the upper byte blocks and the lower byte blocks, as shown in FIG. 2B. If the data input/output lines are commonly occupied, as shown FIG. 2C, the number of the CSL lines connected with the data input/output lines is increased double, which results in a doubled junction loading.